(a) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to the structure of source/drain regions of a MOSFET in the semiconductor device.
(b) Description of the Related Art
A DRAM device generally includes a memory cell area including a plurality of memory cells arranged in a matrix, and a peripheral circuit area in which a peripheral circuit for driving the memory cells are disposed. In recent DRAM devices, MOS transistors include a selective epitaxial silicon layer as the contact layer for the source/drain regions of the MOS transistors in the memory cell area (refer to Patent Publication JP-1995-69446A, for example).
In the semiconductor device described in the above publication, after forming MOS transistors on a semiconductor substrate, an insulating film, and a bottom electrode layer of cell capacitors are formed thereon. Contact holes are then formed penetrating the bottom electrode layer and the insulating layer to expose the source/drain regions. A silicon layer is then deposited using a selective epitaxial growth technique on the surface of the bottom electrode layer and within the contact holes, whereby a contact layer connecting together the source/drain regions and the bottom electrode layer is formed.
In a conventional DRAM device having a 6F2 cell structure, the above epitaxial contact layer is effective to reduce the contact resistance of the memory cells in the memory cell area. However, the epitaxial contact layer is also formed on the source/drain regions of the MOS transistors of the peripheral circuit area. The epitaxial contact layer formed on the source/drain regions of PMOS transistors in the peripheral circuit area may reduce the ON-current (Ion) of the PMOS transistors due to the resistance component of the epitaxial contact layer.
In the conventional DRAM device, the epitaxial contact layer is generally made of titanium silicide (TiSi), and formed on the P+-diffused regions and N+-diffused regions of the MOSFETs. In the mean time, as described in a literature entitled “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS”, in 2004 Symposium on VLSI Technology Digest of Technical Papers, P48-49, and “Layout Impact on the Performance of a Locally Strained PMOSFET”, in 2005 Symposium on VLSI Technology Digest of Technical Papers, P22-23, use of a germanium silicide (SiGe) layer is proposed for improving the ON-current of a PMOS transistor. The SiGe layer is embedded in a recess formed on the P+-type source/drain regions of the PMOS transistor to reduce the compressed strain in the gate electrode of the PMOS transistor and the vicinity thereof in the source/drain regions.
In the proposed structure, however, the process for manufacturing the semiconductor device uses an additional photolithographic step for forming the recess on the surface of the P+-type source/drain regions of the PMOS transistors for receiving the SiGe epitaxial layer. The additional photolithographic step reduces through-put of the semiconductor device and thus increases the costs thereof.